Electrical and electronic communications continue to permeate every aspect of modem life. Computer systems, for example, are becoming increasingly mobile and inter-networked, portable telephones are becoming more ubiquitous, and consumers continue to demand constant access to streaming video, audio, data and other services. As the demand for such services continues to escalate, a need arises for data communications schemes that are space efficient, yet provide rapid data throughput.
Most conventional data signaling schemes used for digital data can be generally classified as “serial” (i.e. providing a stream of sequential data bits across a single channel) or “parallel” (i.e. providing separate streams of data bits across two or more data channels). Serial schemes have the general advantage of being less complicated and more space efficient than parallel schemes due to the single data channel. In particular, the single serial data channel typically uses a minimal number of “pins” on a microchip or similar module. Multiple data paths present in a parallel data channel can consume additional pins and other chip resources, but are generally capable of providing more data at a given transfer rate than a corresponding serial channel. Stated another way, although the serial channels are generally efficient in terms of space and physical overhead, the data rate for a serial channel must typically be faster than that applied to each of the multiple parallel channels for the serial scheme to transfer an equivalent amount of data. While serial transfer schemes are therefore beneficial for many applications (e.g. when space is limited or pin count is a consideration), the bit transfer rates used to obtain acceptable throughput over a serial channel can be significant.
Further, practical serial transfer rates can be hampered by limited availability of high-speed clock sources, speed limitations of transmitting and receiving devices, and/or other factors. As a result, many data signaling schemes now subdivide data messages into distinct “words” that can be simultaneously transmitted across multiple serial data channels. Such a hybrid scheme offers the advantage of reduced pin count compared to traditional parallel schemes along with lower bit rates typically associated with traditional serial schemes without sacrificing total throughput. Difficulties can arise, however, in reconstructing the original message from the collection of independently-recovered serial data words. These difficulties can result from varying path delays (skew) exhibited by the multiple serial channels, which in turn can result from variations in supply voltage, variations in temperature and other environmental effects, and other factors.
Accordingly, it is desirable to formulate a technique for re-synchronizing the multiple serial bitstreams transferred in a multi-pin asynchronous data interface. In addition, it is desirable to create devices and systems for re-synchronizing the serial bitstreams. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.